Quantum Key Distribution Using FPGA

This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins.